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125

XMEGA A [MANUAL]

8077I–AVR–11/2012

12.

Interrupts and Programmable Multilevel Interrupt Controller

12.1

Features

Short and predictable interrupt response time

Separate interrupt configuration and vector address for each interrupt

Programmable multilevel interrupt controller

– Interrupt prioritizing according to level and vector address

– Three selectable interrupt levels for all interrupts: low, medium and high

– Selectable, round-robin priority scheme within low-level interrupts

– Non-maskable interrupts for critical functions

Interrupt vectors optionally placed in the application section or the boot loader section

12.2

Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have

one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it

will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt

controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged

by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are

prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level

interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the

interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest

interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are

serviced within a certain amount of time.

Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.

Figure 12-1. Interrupt controller overview

12.3

Operation

Interrupts must be globally enabled for any interrupts to be generated. This is done by setting the global interrupt enable

( I ) bit in the CPU status register. The I bit will not be cleared when an interrupt is acknowledged. Each interrupt level

must also be enabled before interrupts with the corresponding level can be generated.

When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the interrupt request. Based on

the interrupt level and interrupt priority of any ongoing interrupts, the interrupt is either acknowledged or kept pending

until it has priority. When the interrupt request is acknowledged, the program counter is updated to point to the interrupt

Peripheral 1

Interrupt Controller

INT REQ

INT LEVEL

INT REQ

INT LEVEL

CPU INT REQ

CTRL

LEVEL Enable

CPU.SREG

Global

Interrupt

Enable

Priority

decoder

STATUS

INTPRI

INT ACK

Peripheral n

INT LEVEL

INT REQ

INT ACK

CPU

CPU INT ACK

CPU ”RETI”

Sleep

Controller

Wake-up

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